1. Field of the Invention
The present invention relates to an address translation unit that translates a virtual address to a physical address and, in particular, a translation look-aside buffer (hereinafter referred to as a “TLB”) for address translation in a memory management unit (MMU) that is used along with a central processing unit (CPU) handling a virtual memory system.
2. Description of the Background Art
A CPU handling a virtual memory system outputs a virtual memory address on a logical memory space when the CPU accesses an instruction and data. However, the actual instruction and data are held at a physical address on a physical space. Therefore, an MMU is used to perform translation from the virtual address to the physical address. In this occasion, a TLB contained in the MMU is used to perform high-speed address translation.
As a conventional technique of semiconductor devices using a virtual memory system, for example, Japanese Patent Application Laid-Open No. 4-262436 (columns 1–2, FIGS. 3–4) presents the configuration of an address translation buffer circuit employing a content addressable memory (CAM) cell as a tag part. Specifically, this publication shows such a configuration of comparing a process identification number for identifying the individual space of a multiple virtual storage space with an effective address for access in the tag part.
Meanwhile, Japanese Patent Application Laid-Open No. 7-282587 (columns 13–14, FIG. 4) presents an example of CAM configuration that reduces the parasite capacity of a match line in order to increase the speed of a TLB used for address translation from a virtual address to a physical address.
It is required that address translation from a virtual address to a physical address be performed at high speed. To accomplish this, a number of attempts to increase the speed of address translation, e.g., a reduction in the parasitic capacity of a match line, have been made in the past without great success.